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Introduction The AFE7422 and AFE7444 (AFE74xx) are a family of 4T4R RF sampling transceivers. There are a variety of ways to configure the device in order to achieve required system performance and allocation and to minimize power consumption. The parameters varied are: • Clock frequency – Internal: 5898.24 MHz or 8847.36 MHz – External: 5898.24 MHz to 3500 MHz • Interpolation rate and decimation rate • Number of lanes • Channel count: 2 or 4 • Duplex options: FDD or TDD These parameters are not all independent. Interpolation and decimation rate, sample frequency, number of lanes, and channel count determine appropriate LMFS JESD204B parameters and SerDes speed. For this analysis, the SerDes speed is limited to 10 Gbps or less, and the TX/RX SerDes speeds is kept the same. The relationship to these parameters is: • Fdata = Fs (Sampling Frequency) / INT • Total Bit Rate = Fdata * 16-bits * 10/8 (encoding) * I/Q Channels * # of Channels • Bit Rate per Lane = Total Bit Rate / Number of Lanes. Here is an example calculation with the following parameters: • Fs = 8847.36 MSPS • INT = 18x • 4 I/Q Channels • 8 Lanes The calculations yield: • Fdata = 8847.36 MSPS / 18 = 491.52 MSPS • Total Bit Rate = 491.52 MSPS * 16 * 10/8 * 2 (I/Q) * 4 (Channels) = 78.6432 Gbps • Bit Rate per lane = 78.6432 / 8 = 9.8304 Gbps per lane In this example, the SerDes speed is just at the (artificial) limit. Reducing the speed requires increasing the number of lanes (except the value is already at the limit), or reducing the sampling clock and/or increasing the interpolation/decimation (that is, reducing data rate) or decreasing the channel count. Reducing the data rate decreases bandwidth capability. Reducing sampling clock generally reduces higher-frequency operation. Although these modifications limit the performance capability of the device, the modifications reduce power consumption. The designer has the flexibility to weigh the trade-offs in order to meet system requirements. Official power consumption specifications are outlined in the data sheet. The power consumption parameters used in this analysis were taken on a single device on the AFE7422EVM and AFE7444EVM eva luation modules and may have slight differences due to power management configurations. The primary intent is to provide relative consumption performance across different parameters.
- 两路，14 位 9GSPS DAC
- 高达 1200-MHz 信号带宽
- 每通道 DSA 调节输出功率
- 两路，14 位 3GSPS ADC
- NSD：-152dBFS/Hz
- 交流性能（fIN = 2.6GHz，–3 dBFS）
- SNR：56dBFS
- SFDR：70 dBc HD2 和 HD3
- SFDR：75 dBc（最严重毛刺）
- 孔径抖动：70fs
- 每通道 DSA 扩展 DNR
- 射频和数字功率检测器
- 射频频率范围：30MHz 至 5GHz
- 快速跳频 < 1 µs
- 接收数字信号路径：
- 每个 ADC 有可旁路的四路 DDC
- 每个 DDC 有 3 个相位同调 32 位 NCO
- 抽取率：3 倍 到 32 倍
- 发送数字信号路径：
- 每个 DAC 有使用 32 位 NCO 的四路 DUC
- 插值率：6 倍到 36 倍
- sin(x)/x 校正和可配置延迟
- 功率放大器保护
- JESD204B 接口：
- 8 个高达 15Gbps 的收发器
- 子类 1 多芯片同步
- 时钟:
- 具有旁路选项的内部 PLL/VCO
- 时钟输出高达 3GHz，具有时钟分频器
- DAC 功耗：9GSPS 时为 1.8W/通道
- ADC 功耗：3GSPS 时为 1.9W/通道
- 封装：17mm x 17mm FC BGA，0.8mm 间距